What Is logic OR Gate? Its Symbols, Design Schematics & IC Details
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What Is Logic OR Gate?
The digital logic gate which generates logic True when any of its input is logic True is known as OR gate.
Logic OR gate implements the logical addition. Its output is high even if there is a single high input without caring for the other inputs.
OR gate has 1 output line & it has a minimum of 2 inputs. OR gate is also available with multiple inputs.
Symbol
There are three different symbols used for OR gate.
ANSI
The American National standard Institute symbol, it is most commonly used:
IEC
The International Electrotechnical Commission symbol:
DIN
Deutsches Institut für Normung symbol for OR gate, which is used in Germany:
Truth Table
A logic table containing different combinations of input logic & their corresponding output is called truth table.
Assume 2input OR gate with inputs I_{1}, I_{2} & the output O.
We know that logic OR gate implements logical addition which is the addition of binary numbers 0 & 1.
The logical addition of binary 2 inputs is:
I_{1 }+ I_{2 }= O
0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 1
These combinations can be represented using truthtable as shown below.
Input 
Output 

I_{1}  I_{2}  O 
0  0  0 
0  1  1 
1  0  1 
1  1  1 
Expression
The expression of OR operation uses the symbol (+) or (). Its expression is:
O = I_{1 }+ I_{2 } or O = I_{1 } I_{2}
MultiInput OR Gate
OR gate having more than two inputs is referred as multiinput OR gate.
The output of multiinput OR gate is True when any of its input is logic True or high. It gives output false when all of its inputs are logic false.
We will discuss 3input OR gate for the sake of simplicity. Assume its input I_{1}, I_{2 }& I_{3 }and its output O.
The truth table of 3input OR gate is:
Input  Output  
I_{1}  I_{2}  I_{3}  O 
0  0  0  0 
0  0  1  1 
0  1  0  1 
0  1  1  1 
1  0  0  1 
1  0  1  1 
1  1  0  1 
1  1  1  1 
The expression for 3input OR gate is
O = I_{1} + I_{2 }+ I_{3 } or O = I_{1}  I_{2 } I_{3}
Schematic Design
OR gate has different schematic designs depending on the available components & requirements.
In this article, we will discuss RDL (ResistorDiode Logic) & RTL (ResistorTransistor logic) schematic designs for OR gate briefly.
ResistorDiode Logic
This logic implements any logic function using resistors and diodes. The schematic design of OR gate using RDL logic is given below.
Explanation
There are two diodes whose negative terminal (cathode) is connected in parallel with a resistor. The input I_{1}, I_{2} is applied to the positive terminals (Anod) of the diodes. The resistor R is connected to the ground.
Output O is the voltage developed across the resistor R.
The input logic True or High is 5v & false or Low is 0v or ground.
We will discuss this schematic for each of the input combinations.
Case 1
The first case is when both inputs are low i.e. I_{1 }& I_{2 }= 0v = ground. The schematic for such case is:
Logic 0 or Ground is applied as input I_{1 }& I_{2 }to the positive terminals of the diodes. Thus the diodes become reversed biased (switched off) & they don’t allow the flow of any current. Due to which, there is no voltage drop across R.
So the output voltage O will be zero volts, which is the voltage drop across resistor R. Thus the output is logic low or 0.
Case 2
Another case is when one of the input I_{1 }or I_{2 }is true i.e. I_{1} = 0v & I_{2 }= 5v.
Logic 0 or ground applied to one of the diodes will still remain reversed biased (switched off). However, logic true or 5v to the positive terminal of the other diode will make it forward bias (switched on). Due to this one diode, the path for the flow of current will complete & there will be voltage developed across resistor R.
This voltage drop is taken as output O, which is logic true or high in this case.
Case 3
The last one is when both of the inputs are logic true or high I.e. I_{1} & I_{2 }= 5v. The schematic will operate as:
When logic high of 5v is applied to the positive terminal of the diode, both of the diodes will become forward biased (switched on). This will complete the current flow path. The current flow through the circuit will result in the voltage drop across the resistor R.
The voltage drop across R is the output logic True of the OR gate.
ResistorTransistor Logic
This logic uses resistors & transistors to implement any logic function. The logic OR gate schematic design using RTL is given below:
Explanation
In this schematic, two NPN transistors are connected in parallel with each other. The collector of the NPNs are connected with 5v Vs & the emitter is connected to resistor R, which is connected to the ground.
The input is applied to the gates of the NPN transistors & the output is taken across the resistor R.
This schematic operates on 5v as supply voltage Vs. The input True logic is 5v & false logic is 0v or ground.
Now we will discuss this schematic for each combination of input logic.
Case 1
The first case is when both inputs are logic false or low i.e. I_{1 }& I_{2 }= 0v.
Note: NPN transistor switches on when its gate input is logic True or High & switches off when the gate input is logic false or low.
In this case, the inputs are logic low. So the ground is connected to the gates of the transistors. Due to which, the transistor switches off & the path for the flow of current breaks. As there is no current flow through the circuit, there will be no potential developed across resistor R.
The potential developed across resistor R is the output of this schematic, which is 0v. thus the output is Logic Low or False.
Case 2
The second case is then one of the input is logical true & the other is false i.e. I_{1 }= 0v & I_{2 }= 5v.
In such case, one of the NPN transistors is switched on whose gate input is logic True or 5v. However, the transistor remains switched off but the path for the current flow is completed due to the switchedon transistor. There is a current flow through the circuit. Due to which, there is a potential developed across resistor R.
This potential is the output of the OR gate which is logic True or High.
Case 3
The lase case is when both inputs are true or high i.e. I_{1 }& I_{2 }= 5v. The schematic will operate as:
In this case, both of the transistors are switched on because their gate input is logic True or High. The current flow path is complete through both transistors. Due to the current flow, there is a voltage drop across the resistor R.
The voltage drop across resistor R is the output of the OR gate. Which is logic true or high.
Construction From Universal Gates
Universal gates are those logic gates which can be used to implement any logic function. The universal gates ate NAND gate & NOR gate.
Construction From NAND Gate
The Boolean expression for NAND gate is:
NAND operation = (I_{1 }. I_{2})’
The implementation of OR gate using NAND gate is possible if we follow the expression below:
O = {(I_{1 }. I_{1})’ . (I_{2 }. I_{2})’ }’
O = {(I_{1})’ . (I_{2})’ }’
O = I_{1} + I_{2}
So the OR gate implementation design using NAND gate is:
Construction From NOR Gate
The expression of NOR gate is:
(I_{1 }+ I_{2})’ = NOR operation
The OR gate is the inverse of NOR gate or vice versa.
O = (I_{1 }+ I_{2})’ ‘
O = I_{1 }+ I_{2}
So if we use another NOR gate as an Inverter, we can get an OR gate’s output as shown in the figure below:
OR Gate IC
The pin configuration of OR gate IC is given below:
Pin  Detail 
1  Input 1 Gate 1 
2  Input 2 Gate 1 
3  Output Gate 1 
4  Output Gate 2 
5  Input 1 Gate 2 
6  Input 2 Gate 2 
7  Vss, ground 
8  Input 1 Gate 3 
9  Input 2 Gate 3 
10  Output Gate 3 
11  Output Gate 4 
12  Input 1 Gate 4 
13  Input 2 Gate 4 
14  Voltage Supply Vdd 
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