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Digital Logic NOR Gate (Universal Gate), Its Symbols, Schematic Designs & IC Details

What Is Digital Logic NOR Gate (Universal GATE)? its Symbols, Design Schematics & IC Details 

Digital Logic NOR Gate

The digital logic gate which generates logic False when any of its input logic is True is known as NOR gate.

Digital Logic NOR Gate (Universal Gate), Its Symbols, Schematic Designs & IC Details

NOR gate is a universal gate capable of implementing any possible logic function. This property of implementing any logic function makes it a universal gate.

NOR gate has a minimum of 2 inputs and can have more than 2 inputs but it has only a single output.

What is a universal Gate?

universal gate is such kind of logic gate which can be used to implement any kind of logic function hence the name universal logic gate.

NOR gate is one of the universal gates as it can be used to implement any logic function considering basic or complex functions. Basic logic gates such as ANDOR, NOT etc. can be easily implemented using only NOR gate.

Symbols:

There are three different symbols used for NOR gate.

ANSI Symbol

The American National standard Institute symbol, it is most commonly used:

NOR Gate ANSI Symbol

IEC Symbol

The International Electrotechnical Commission symbol:

NOR Gate IEC Symbol

DIN Symbol

Deutsches Institut für Normung symbol for NOR gate, which is used in Germany:

NOR Gate DIN Symbol

Truth Table:

The truth table is a logic table which contains the input logic combinations with their respective output logic. It is easy to read and understand.

Assume a 2-input NOR gate with inputs I1, I& output O. The truth table for such NOR gate is:

Input Output
I1 I2 O
0 0 1
0 1 0
1 0 0
1 1 0

Expression

The expression for NOR gate is the same as OR gate but with a negation bar( ̅ ) on top as shown in the expressions below:

O = (I1 + I2)’               or            O = (I|| I2)’

The () complement sign shows an inverted output.

Multi-Input NOR Gate

NOR gate is also available with more than two inputs, such gate is usually known as multi-input NOR gate.

The Output of multi-input NOR gate is False when any of its inputs are logic True.

Multi-Input NOR Gate Symbol

Assume 3-input NOR gate with input I1, I2, I3 & its output O.

Then the truth table of this 3-input NOR gate is:

 

Input Output
I1 I2 I3 O
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0

And the expression of 3-input NOR gate will be:

O = (I­1 + I+ I3)’         or            O = (I­1 || I|| I3)’

Schematic Designs

There are several schematic designs used for NOR gate. We will discuss the basic and most prominent schematic designs in this article including RTL (Resistor-Transistor logic) & MOS logic.

Resistor-Diode Logic (RDL)

RDL logic comprises resistors and diodes to perform some logic function. However, diodes cannot invert any input signal so it is impossible to design NOR gate using this logic.

Resistor-Transistor Logic (RTL)

RTL logic uses resistors and transistor (BJT) to implement any logic function. The BJTsare used as a switching device to control the current flow. The schematic of NOR gate in RTL logic is given below:

RTL NOR Gate Schematic

This schematic operates on the 5v supply Vcc. The input logic True & False is 5v and 0v respectively.

In this schematic, the NPN transistors are used in parallel such that the emitter & collector of one NPN transistor is connected with the emitter & transistor of the other transistor respectively. The collector of these both transistors is connected with resistor R3, which is connected with supply input Vcc. And their emitter is connected with GND.

The input logic I1, Iis applied to the base of these transistors through resistor R& R2 respectively. The output is taken across resistor Rand the collectors of NPN.

We will discuss the working of this schematic for each input combinations.

Case 1

When both of the input is logical low i.e. I1 & I= 0v.

RTL NOR Gate Schematic case 1

Note: the NPN transistor activates when there is base current. The base current is produced due to High input logic. So the NPN switches ON when the input is logic High & it switches OFF when the input is logic Low.

Due to input logic Low, the transistor will switch off and they will cut off the current flow path from Vcc to GND. And a conductive path from Vcc to output is established, through which the logic high output flows out as output.

Case 2

The second case is when one of the input is Low & the other is High i.e. I= 5v & I­= 0v. The schematic will operate as shown below:

RTL NOR Gate Schematic case 2

The Low input will switch off the NPN transistors and the high input will turn ON the transistor.

A current flow path will be established from Vcc to GND because one of the transistors is switched ON. This in turn set up a short path between GND & output. So GND as logic Low will flow out as the output of this schematic.

Case 3

When both of the inputs are logic High i.e. I& I= 5v. The schematic will operate as :

RTL NOR Gate Schematic case 3

As both of the inputs are High, so the transistor connected to them will switch ON & provide a current path from Vcc to GND. In such case, the output becomes directly connected to the ground GND. In result, GND as logic Low flow through as output.

MOS Logic

MOS logic uses Mosfets as the switching devices to implement any logic function. Mosfets such as NMOSPMOS & CMOS are used in these designs. Mosfets are more economical because of their small sizes & low power consumption. It operates on input voltages. On the contrary, BJT operates on input current.

NMOS Design

The schematic design of NOR gate using NMOS transistor is given below:

NMOS NOR Gate Schematic

This NOR gate design using Two NMOS shows that they are connected together in parallel & the drain of both NMOS is connected to a resistor R, which is connected to supply voltage Vdd. The source of these both NMOS transistors is connected to ground.

Input is directly applied to its gate, it does not need input resistor because it operates on input voltage rather than the input current.

The output is taken between the resistor R & the drain of the NMOS.

NOTE: NMOS switch on when input logic is High & it switches off when input logic is Low.

Case 1

When both of the input logic is Low i.e. I& I= 0v, both NMOS switches OFF & the current path from Vdd to GND breaks & a conducting path from Vdd to Output is established. Thus the output becomes Vdd, which is logic High.

NMOS NOR Gate Schematic case 1

Case 2

The second case is when one of the input is High and the other is Low i.e. I1 = 0v & I2= 5v. The NMOS having High gate input switches ON and the other NMOS switches OFF as its gate input is Low.

But the current path is established because one of the NMOS is switched ON. As a result, the output becomes directly connected to GND, which becomes the output of the NOR gate as logic LOW.

NMOS NOR Gate Schematic case 2

Case 3

When both of the input is High i.e. I& I= 5v. Both NMOS will switch ON because their gate input is logic High. The path for the flow of current from Vdd to GND completes resulting in a direct path between GND and output. So the output becomes Logic Low.

NMOS NOR Gate Schematic case 3

PMOS Design

The design schematic of NOR gate using PMOS is given below:

PMOS NOR Gate Schematic

In this design, the two PMOS are connected in Series such that the Source of first PMOS is connected to the drain of the second PMOS. The drain of the first PMOS is directly connected to the supply voltage Vdd & the source of the second PMOS is connected to resistor R, which is connected to GND.

Input I1, I2 is applied to the gates of PMOS & the output is taken across the resistor R.

NOTE: PMOS switches on when its gate input is logic Low & it switches off when gate input is logic High.

Case 1

When both of the input is logic Low i.e. I& I= 0v.

PMOS NOR Gate Schematic case 1

Both of the PMOS will switch ON as their gate input is logic Low, resulting in creating a path for the flow of current from Vdd to GND. As a result, a direct path between Vdd output is established. Thus the output O becomes logic High.

Case 2

When one of the input is logic high and the other is logic Low i.e. I1 = 0v & I= 5v.

PMOS NOR Gate Schematic case 2

The PMOS having High gate input switches OFF and the other PMOS switch ON as its gate input is Low. Thus the current conducting path from Vdd to GND breaks and the GND becomes directly connected to the output.

Thus the output becomes logic Low.

Case 3

When both of the inputs is logic High i.e. I& I= 5v.

 PMOS NOR Gate Schematic case 3

Both of the PMOS switches OFF because their gate input is logic Low. As a result, the current path from Vdd to GND breaks & the GND becomes directly connected to the output. Thus resulting in output logic Low.

CMOS Logic

CMOS (Complementary metal oxide semiconductor) is mostly used in designing a variety of logic circuit as they are most economical,

The design of NOR gate using CMOS is given below:

CMOS NOR Gate Schematic

In this design, NMOS & PMOS are both used together.

PMOS part is known as Pull-Up Network (PUN) & NMOS part is known as Pull-Down Network (PDN).

In the Pull-up network part, two PMOS are connected in series. The source of one NMOS is connected with the drain of the second PMOS & the Drain of first PMOS is directly connected to the Vdd.

In Pull-down network part, two NMOS are connected in parallel with each other whose source is connected to the GND.

These both networks are connected together as shown in the figure above. The gate of one PMOS and NMOS is connected together to make one input & the output is taken between these two networks (PUN & PDN).

Case 1

When both of the input is logic Low i.e. I& I= 0v.

CMOS NOR Gate Schematic case 1

The PMOS will switch ON & NMOS will switch OFF. Only the pull-up network (PUN) activates & As a result, it creates a conductive path from the Vdd to the Output. Due to which, the output becomes logic High.

Case 2

When one of the input is logic high and the other is logic Low i.e. I1 = 0v & I= 5v.

CMOS NOR Gate Schematic case 2

In this case, one PMOS & one NMOS will switch ON in both PUN & PDN network. It will result in activating only the pull-down network (PDN) because of the activated NMOS in parallel. This configuration results in a direct path from GND to output. Due to which the output becomes logic Low.

Case 3

When both of the input is logic High i.e. I& I= 5v

CMOS NOR Gate Schematic case 3

The PMOS will switch OFF & the NMOS will switch ON because their gate input is logic High. As a result, only the Pull-down network (PDN) activates which creates a direct path from GND to output. Thus the output becomes logic Low.

NOR Gate IC

The pin configuration of NOR gate IC is given below:

NOR Gate IC

Pin Detail
1 Input 1 Gate 1
2 Input 2 Gate 1
3 Output Gate 1
4 Output Gate 2
5 Input 1 Gate 2
6 Input 2 Gate 2
7 Vss, ground
8 Input 1 Gate 3
9 Input 2 Gate 3
10 Output Gate 3
11 Output Gate 4
12 Input 1 Gate 4
13 Input 2 Gate 4
14 Voltage Supply Vdd

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