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Digital Logic NAND Gate (Universal Gate), Its Symbols, Schematic Designs & IC Details

What Is Digital Logic NAND Gate (Universal GATE)? its Symbols, Design Schematics & IC Details 

Digital Logic NAND Gate (Universal Gate):

The digital logic gate which gives output False only when all of its input are True or it gives output True when any of its input is low.

Digital Logic NAND Gate (Universal Gate), Its Symbols, Schematic Designs & IC Details

NAND gate in the NOT (Invert) of AND gate. It basically gives the complemented output of AND gate. It is a universal gate. NAND gate can have two or more than two inputs, but it has only one output.

Why Universal Gate?

A universal gate is such kind of logic gate which can be used to implement any kind of logic function hence the name universal logic gate.

NAND gate is one of the universal gates as it can be used to implement any logic function considering basic or complex functions. Basic logic gates such as AND, OR, NOT etc. can be easily implemented using only NAND gate.

Symbols:

There are three different symbols used for NAND gate.

ANSI Symbol

The American National standard Institute symbol, it is most commonly used:

NAND Gate ANSI Symbol

IEC Symbol

The International Electrotechnical Commission symbol:

NAND Gate IEC Symbol

DIN Symbol

Deutsches Institut für Normung symbol for NAND gate, which is used in Germany:

NAND Gate DIN Symbol

Truth table:

The truth table is a logic table which contains the input logic combinations with their respective output. It is easy to read and understand.

Assume a 2-input NAND gate with inputs I1, I2 & output O. The truth table for such NAND gate is:

Input Output
I1 I2 O
0 0 1
0 1 1
1 0 1
1 1 0

Expression

The expression for NAND gate is same as AND gate but with a negation bar( ̅ ) on top as shown in the expressions below:

O = (I1 . I2)’               or            O = (I1 & I2)’

the () complement sign shows inverted output.

Multi-Input NAND Gate

NAND gate is also available with more than two inputs, such gate is usually known as multi-input NAND gate.

The Output of multi-input NAND gate is False when all of its inputs are logic True.

Assume 3-input NAND gate with input I1, I2, I3 & its output O.

Multi-Input NAND Gate Symbol

Then the truth table of this 3-input NAND gate is:

 

Input Output
I1 I2 I3 O
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

And the expression of 3-input NAND gate will be:

O = (I­1 . I2 . I3)’         or            O = (I­1 & I2 & I3)’

Schematic Designs

There are several schematic designs used for NAND gate. We will discuss the basic and most prominent schematic designs in this article including RTL (Resistor-Transistor logic) & MOS logic.

Resistor-Diode Logic (RDL)

RDL logic comprises resistors and diodes to perform some logic function. However, diodes cannot invert any input signal so it is impossible to design NAND gate using this logic.

Resistor-Transistor Logic (RTL)

RTL logic uses resistors and transistor (BJT) to implement any logic function. The BJTs are used as a switching device to control the current flow. The schematic of NAND gate in RTL logic is given below:

RTL NAND Gate Schematic

This schematic operates on the 5v supply Vcc. The input logic True & False is 5v and 0v respectively.

In this schematic, the NPN transistors are used in series such that the emitter of one NPN transistor is connected with the collector of the other transistor. The collector of the first transistor is connected with resistor R3, which is connected with supply input Vcc. The emitter of the second transistor is connected with GND.

The input logic I1, I2 is applied to the base of these transistors through resistor R1 & R2 respectively. The output is taken across resistor R3 and the collector of the first transistor.

We will discuss the working of this schematic for each input combinations.

Case 1

When both of the input is logical low i.e. I1 & I2 = 0v.

RTL NAND Gate Schematic case 1

Note: the NPN transistor activates when there is base current. The base current is produced due to High input logic. So the NPN switches ON when the input is logic High & it switches OFF when the input is logic Low.

Due to input logic Low, the transistor will switch off and they will cut off the current flow path. A conductive path from Vcc to output is established, through which the logic high output flows out as output.

Case 2

The second case is when one of the input is Low & the other is High i.e. I1 = 5v &2 = 0v. The schematic will operate as shown below:

RTL NAND Gate Schematic case 2

The Low input will switch off the NPN transistors and the high input will turn ON the transistor.

The current flow path is still broken because of the logic low input and the path to the output is established between Vcc & output. So Vcc as logic High will flow out as the output of this schematic.

Case 3

When both of the inputs are logic High i.e. I1 & I2 = 5v. the schematic will operate as :

RTL NAND Gate Schematic case 3

As both of the inputs are High, so the transistor connected to them will switch ON & provide a current path from Vcc to GND. In such case, the output becomes directly connected to the ground GND. In result, logic Low flow through as output.

MOS Logic

MOS logic uses Mosfets as the switching devices to implement any logic function. Mosfets such as NMOS, PMOS & CMOS are used in these designs. Mosfets are more economical because of their small sizes & low power consumption. It operates on input voltages. on the contrary, BJT operates on input current.

NMOS Design

The schematic design of NAND gate using NMOS transistor is given below:

NMOS NAND Gate Schematic

This NAND gate design using Two NMOS shows that they are connected together in series & the drain of first NMOS is connected to a resistor R, which is connected to supply voltage Vdd. The source of the second NMOS is connected to ground.

Input is directly applied to its gate, it does not need input resistor because it operates on input voltage rather than the input current.

The output is taken between the resistor R & the drain of the first NMOS.

NOTE: NMOS switch on when input logic is High & it switches off when input logic is Low.

Case 1

When both of the input logic is Low i.e. I1 & I2 = 0v, both NMOS switches OFF & the current path from Vdd to GND breaks & a conducting path from Vdd to Output is established. Thus the output becomes Vdd, which is logic High.

NMOS NAND Gate Schematic case 1

Case 2

The second case is when one of the input is High and the other is Low i.e. I1 = 0v & I2 = 5v. The NMOS having High gate input switches ON and the other NMOS switches OFF as its gate input is Low.

Thus the current path breaks and the output becomes connected to Vdd, which is the output of the NAND gate.

NMOS NAND Gate Schematic case 2

Case 3

When both of the input is High i.e. I1 & I2 = 5v. Both NMOS will switch ON because their gate input is logic High. The path for the flow of current from Vdd to GND completes resulting in a direct path between GND and output. So the output becomes Logic Low.

NMOS NAND Gate Schematic case 3

PMOS Design

The design schematic of NAND gate using PMOS is given below:

PMOS NAND Gate Schematic

In this design, the two PMOS are connected in parallel with each other. The drain of the PMOS is directly connected to the supply voltage Vdd & the source is connected to resistor R, which is connected to GND.

Input is applied through the gate & the output is taken between the source & resistor R.

NOTE: PMOS switches on when its gate input is logic Low & it switches off when gate input is logic High.

Case 1

When both of the input is logic Low i.e. I1 & I2 = 0v.

PMOS NAND Gate Schematic case 1

Both of the PMOS will switch ON as their gate input is logic Low, resulting in creating a path for the flow of current from Vdd to GND. As a result, a direct path between Vdd & output is established. Thus the output O becomes logic High.

Case 2

When one of the input is logic high and the other is logic Low i.e. I1 = 0v & I2 = 5v.

PMOS NAND Gate Schematic case 2

The PMOS having High gate input switches OFF and the other PMOS switch ON as its gate input is Low. But still, the path is complete from Vdd to GND.

So the output will still be connected to Vdd, which means that the output is logic High.

Case 3

When both of the inputs is logic High i.e. I1 & I2 = 5v.

PMOS NAND Gate Schematic case 3

The PMOS switches OFF because their gate input is logic Low. As a result, the current path from Vdd to GND breaks & the GND becomes directly connected to the output. Thus resulting in output logic Low.

CMOS Logic

CMOS (Complementary metal oxide semiconductor) is mostly used in designing a variety of logic circuit as they are most economical,

The design of NAND gate using CMOS is given below:

CMOS NAND Gate Schematic

In this design, NMOS & PMOS are both used together.

PMOS part is known as Pull-Up Network (PUN) & NMOS part is known as Pull-Down Network (PDN).

In Pull-up network part, two PMOS are connected in parallel with each other whose drain is connected to supply voltage Vdd.

In Pull-down network part, two NMOS are connected in series. The source of one NMOS is connected with the drain of the second NMOS & the Source of second NMOS is directly connected to the GND.

These both networks are connected together as shown in the figure above. The gate of one PMOS and NMOS is connected together to make one input & the output is taken between these two networks (PUN & PDN).

Case 1

When both of the input is logic Low i.e. I1 & I2 = 0v.

CMOS NAND Gate Schematic case 1

The PMOS will switch ON & NMOS will switch OFF. Only the pull-up network (PUN) activates & the pull-dewn network (PDN) breaks the path between Vdd & GND. As a result, it creates a conductive path from the Vdd to the Output. Due to which, the output becomes logic High.

Case 2

When one of the input is logic high and the other is logic Low i.e. I1 = 0v & I2 = 5v.

CMOS NAND Gate Schematic case 2

In this case, one PMOS & one NMOS will switch ON. It will result in activating only the pull-up network (PUN) which means a direct path from Vdd to output. As a result, the output becomes logic High.

Case 3

When both of the input is logic High i.e. I1 & I2 = 5v

CMOS NAND Gate Schematic case 3

The PMOS will switch OFF because the gate input is High & the NMOS will switch ON as their gate input is logic High. As a result, only Pull-down network (PDN) activates which creates a direct path from GND to output. Thus the output becomes logic Low.

IC Details

Pin configuration with details of NAND gate IC is given below:

 

NAND Gate IC

Pin Detail
1 Input 1 Gate 1
2 Input 2 Gate 1
3 Output Gate 1
4 Input 1 Gate 2
5 Input 2 Gate 2
6 Output Gate 2
7 Ground
8 Output Gate 3
9 Input 1 Gate 3
10 Input 2 Gate 3
11 Output Gate 4
12 Input 1 Gate 4
13 Input 2 Gate 4
14 Voltage Supply Vdd

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