The post Digital Logic NOR Gate (Universal Gate), Its Symbols, Schematic Designs & IC Details appeared first on Electronics Engineering.
]]>The digital logic gate which generates logic False when any of its input logic is True is known as NOR gate.
NOR gate is a universal gate capable of implementing any possible logic function. This property of implementing any logic function makes it a universal gate.
NOR gate has a minimum of 2 inputs and can have more than 2 inputs but it has only a single output.
A universal gate is such kind of logic gate which can be used to implement any kind of logic function hence the name universal logic gate.
NOR gate is one of the universal gates as it can be used to implement any logic function considering basic or complex functions. Basic logic gates such as AND, OR, NOT etc. can be easily implemented using only NOR gate.
There are three different symbols used for NOR gate.
The American National standard Institute symbol, it is most commonly used:
The International Electrotechnical Commission symbol:
Deutsches Institut für Normung symbol for NOR gate, which is used in Germany:
The truth table is a logic table which contains the input logic combinations with their respective output logic. It is easy to read and understand.
Assume a 2input NOR gate with inputs I_{1}, I_{2 }& output O. The truth table for such NOR gate is:
Input  Output  
I_{1}  I_{2}  O 
0  0  1 
0  1  0 
1  0  0 
1  1  0 
The expression for NOR gate is the same as OR gate but with a negation bar( ̅ ) on top as shown in the expressions below:
O = (I_{1} + I_{2})’ or O = (I_{1 } I_{2})’
The (‘) complement sign shows an inverted output.
NOR gate is also available with more than two inputs, such gate is usually known as multiinput NOR gate.
The Output of multiinput NOR gate is False when any of its inputs are logic True.
Assume 3input NOR gate with input I_{1}, I_{2}, I_{3} & its output O.
Then the truth table of this 3input NOR gate is:
_{ }
Input  Output  
I_{1}  I_{2}  I_{3}  O 
0  0  0  1 
0  0  1  0 
0  1  0  0 
0  1  1  0 
1  0  0  0 
1  0  1  0 
1  1  0  0 
1  1  1  0 
And the expression of 3input NOR gate will be:
O = (I_{1} + I_{2 }+ I_{3})’ or O = (I_{1}  I_{2 } I_{3})’
There are several schematic designs used for NOR gate. We will discuss the basic and most prominent schematic designs in this article including RTL (ResistorTransistor logic) & MOS logic.
RDL logic comprises resistors and diodes to perform some logic function. However, diodes cannot invert any input signal so it is impossible to design NOR gate using this logic.
RTL logic uses resistors and transistor (BJT) to implement any logic function. The BJTsare used as a switching device to control the current flow. The schematic of NOR gate in RTL logic is given below:
This schematic operates on the 5v supply Vcc. The input logic True & False is 5v and 0v respectively.
In this schematic, the NPN transistors are used in parallel such that the emitter & collector of one NPN transistor is connected with the emitter & transistor of the other transistor respectively. The collector of these both transistors is connected with resistor R3, which is connected with supply input Vcc. And their emitter is connected with GND.
The input logic I_{1}, I_{2 }is applied to the base of these transistors through resistor R_{1 }& R_{2 }respectively. The output is taken across resistor R_{3 }and the collectors of NPN.
We will discuss the working of this schematic for each input combinations.
Case 1
When both of the input is logical low i.e. I_{1} & I_{2 }= 0v.
Due to input logic Low, the transistor will switch off and they will cut off the current flow path from Vcc to GND. And a conductive path from Vcc to output is established, through which the logic high output flows out as output.
Case 2
The second case is when one of the input is Low & the other is High i.e. I_{1 }= 5v & I_{2 }= 0v. The schematic will operate as shown below:
The Low input will switch off the NPN transistors and the high input will turn ON the transistor.
A current flow path will be established from Vcc to GND because one of the transistors is switched ON. This in turn set up a short path between GND & output. So GND as logic Low will flow out as the output of this schematic.
Case 3
When both of the inputs are logic High i.e. I_{1 }& I_{2 }= 5v. The schematic will operate as :
As both of the inputs are High, so the transistor connected to them will switch ON & provide a current path from Vcc to GND. In such case, the output becomes directly connected to the ground GND. In result, GND as logic Low flow through as output.
MOS logic uses Mosfets as the switching devices to implement any logic function. Mosfets such as NMOS, PMOS & CMOS are used in these designs. Mosfets are more economical because of their small sizes & low power consumption. It operates on input voltages. On the contrary, BJT operates on input current.
The schematic design of NOR gate using NMOS transistor is given below:
This NOR gate design using Two NMOS shows that they are connected together in parallel & the drain of both NMOS is connected to a resistor R, which is connected to supply voltage Vdd. The source of these both NMOS transistors is connected to ground.
Input is directly applied to its gate, it does not need input resistor because it operates on input voltage rather than the input current.
The output is taken between the resistor R & the drain of the NMOS.
Case 1
When both of the input logic is Low i.e. I_{1 }& I_{2 }= 0v, both NMOS switches OFF & the current path from Vdd to GND breaks & a conducting path from Vdd to Output is established. Thus the output becomes Vdd, which is logic High.
Case 2
The second case is when one of the input is High and the other is Low i.e. I_{1} = 0v & I_{2}= 5v. The NMOS having High gate input switches ON and the other NMOS switches OFF as its gate input is Low.
But the current path is established because one of the NMOS is switched ON. As a result, the output becomes directly connected to GND, which becomes the output of the NOR gate as logic LOW.
Case 3
When both of the input is High i.e. I_{1 }& I_{2 }= 5v. Both NMOS will switch ON because their gate input is logic High. The path for the flow of current from Vdd to GND completes resulting in a direct path between GND and output. So the output becomes Logic Low.
The design schematic of NOR gate using PMOS is given below:
In this design, the two PMOS are connected in Series such that the Source of first PMOS is connected to the drain of the second PMOS. The drain of the first PMOS is directly connected to the supply voltage Vdd & the source of the second PMOS is connected to resistor R, which is connected to GND.
Input I_{1}, I_{2} is applied to the gates of PMOS & the output is taken across the resistor R.
Case 1
When both of the input is logic Low i.e. I_{1 }& I_{2 }= 0v.
Both of the PMOS will switch ON as their gate input is logic Low, resulting in creating a path for the flow of current from Vdd to GND. As a result, a direct path between Vdd & output is established. Thus the output O becomes logic High.
Case 2
When one of the input is logic high and the other is logic Low i.e. I_{1} = 0v & I_{2 }= 5v.
The PMOS having High gate input switches OFF and the other PMOS switch ON as its gate input is Low. Thus the current conducting path from Vdd to GND breaks and the GND becomes directly connected to the output.
Thus the output becomes logic Low.
Case 3
When both of the inputs is logic High i.e. I_{1 }& I_{2 }= 5v.
Both of the PMOS switches OFF because their gate input is logic Low. As a result, the current path from Vdd to GND breaks & the GND becomes directly connected to the output. Thus resulting in output logic Low.
CMOS (Complementary metal oxide semiconductor) is mostly used in designing a variety of logic circuit as they are most economical,
The design of NOR gate using CMOS is given below:
In this design, NMOS & PMOS are both used together.
PMOS part is known as PullUp Network (PUN) & NMOS part is known as PullDown Network (PDN).
In the Pullup network part, two PMOS are connected in series. The source of one NMOS is connected with the drain of the second PMOS & the Drain of first PMOS is directly connected to the Vdd.
In Pulldown network part, two NMOS are connected in parallel with each other whose source is connected to the GND.
These both networks are connected together as shown in the figure above. The gate of one PMOS and NMOS is connected together to make one input & the output is taken between these two networks (PUN & PDN).
Case 1
When both of the input is logic Low i.e. I_{1 }& I_{2 }= 0v.
The PMOS will switch ON & NMOS will switch OFF. Only the pullup network (PUN) activates & As a result, it creates a conductive path from the Vdd to the Output. Due to which, the output becomes logic High.
Case 2
When one of the input is logic high and the other is logic Low i.e. I_{1} = 0v & I_{2 }= 5v.
In this case, one PMOS & one NMOS will switch ON in both PUN & PDN network. It will result in activating only the pulldown network (PDN) because of the activated NMOS in parallel. This configuration results in a direct path from GND to output. Due to which the output becomes logic Low.
Case 3
When both of the input is logic High i.e. I_{1 }& I_{2 }= 5v
The PMOS will switch OFF & the NMOS will switch ON because their gate input is logic High. As a result, only the Pulldown network (PDN) activates which creates a direct path from GND to output. Thus the output becomes logic Low.
The pin configuration of NOR gate IC is given below:
Pin  Detail 
1  Input 1 Gate 1 
2  Input 2 Gate 1 
3  Output Gate 1 
4  Output Gate 2 
5  Input 1 Gate 2 
6  Input 2 Gate 2 
7  Vss, ground 
8  Input 1 Gate 3 
9  Input 2 Gate 3 
10  Output Gate 3 
11  Output Gate 4 
12  Input 1 Gate 4 
13  Input 2 Gate 4 
14  Voltage Supply Vdd 
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]]>The post Digital Logic NAND Gate (Universal Gate), Its Symbols, Schematic Designs & IC Details appeared first on Electronics Engineering.
]]>The digital logic gate which gives output False only when all of its input are True or it gives output True when any of its input is low.
NAND gate in the NOT (Invert) of AND gate. It basically gives the complemented output of AND gate. It is a universal gate. NAND gate can have two or more than two inputs, but it has only one output.
A universal gate is such kind of logic gate which can be used to implement any kind of logic function hence the name universal logic gate.
NAND gate is one of the universal gates as it can be used to implement any logic function considering basic or complex functions. Basic logic gates such as AND, OR, NOT etc. can be easily implemented using only NAND gate.
There are three different symbols used for NAND gate.
The American National standard Institute symbol, it is most commonly used:
The International Electrotechnical Commission symbol:
Deutsches Institut für Normung symbol for NAND gate, which is used in Germany:
The truth table is a logic table which contains the input logic combinations with their respective output. It is easy to read and understand.
Assume a 2input NAND gate with inputs I_{1}, I_{2 }& output O. The truth table for such NAND gate is:
Input  Output  
I_{1}  I_{2}  O 
0  0  1 
0  1  1 
1  0  1 
1  1  0 
The expression for NAND gate is same as AND gate but with a negation bar( ̅ ) on top as shown in the expressions below:
O = (I_{1} . I_{2})’ or O = (I_{1 }& I_{2})’
the (‘) complement sign shows inverted output.
NAND gate is also available with more than two inputs, such gate is usually known as multiinput NAND gate.
The Output of multiinput NAND gate is False when all of its inputs are logic True.
Assume 3input NAND gate with input I_{1}, I_{2}, I_{3} & its output O.
Then the truth table of this 3input NAND gate is:
_{ }
Input  Output  
I_{1}  I_{2}  I_{3}  O 
0  0  0  1 
0  0  1  1 
0  1  0  1 
0  1  1  1 
1  0  0  1 
1  0  1  1 
1  1  0  1 
1  1  1  0 
And the expression of 3input NAND gate will be:
O = (I_{1} . I_{2 }. I_{3})’ or O = (I_{1} & I_{2 }& I_{3})’
There are several schematic designs used for NAND gate. We will discuss the basic and most prominent schematic designs in this article including RTL (ResistorTransistor logic) & MOS logic.
RDL logic comprises resistors and diodes to perform some logic function. However, diodes cannot invert any input signal so it is impossible to design NAND gate using this logic.
RTL logic uses resistors and transistor (BJT) to implement any logic function. The BJTs are used as a switching device to control the current flow. The schematic of NAND gate in RTL logic is given below:
This schematic operates on the 5v supply Vcc. The input logic True & False is 5v and 0v respectively.
In this schematic, the NPN transistors are used in series such that the emitter of one NPN transistor is connected with the collector of the other transistor. The collector of the first transistor is connected with resistor R3, which is connected with supply input Vcc. The emitter of the second transistor is connected with GND.
The input logic I_{1}, I_{2 }is applied to the base of these transistors through resistor R_{1 }& R_{2 }respectively. The output is taken across resistor R_{3 }and the collector of the first transistor.
We will discuss the working of this schematic for each input combinations.
Case 1
When both of the input is logical low i.e. I_{1} & I_{2 }= 0v.
Due to input logic Low, the transistor will switch off and they will cut off the current flow path. A conductive path from Vcc to output is established, through which the logic high output flows out as output.
Case 2
The second case is when one of the input is Low & the other is High i.e. I_{1 }= 5v & I_{2 }= 0v. The schematic will operate as shown below:
The Low input will switch off the NPN transistors and the high input will turn ON the transistor.
The current flow path is still broken because of the logic low input and the path to the output is established between Vcc & output. So Vcc as logic High will flow out as the output of this schematic.
Case 3
When both of the inputs are logic High i.e. I_{1 }& I_{2 }= 5v. the schematic will operate as :
As both of the inputs are High, so the transistor connected to them will switch ON & provide a current path from Vcc to GND. In such case, the output becomes directly connected to the ground GND. In result, logic Low flow through as output.
MOS logic uses Mosfets as the switching devices to implement any logic function. Mosfets such as NMOS, PMOS & CMOS are used in these designs. Mosfets are more economical because of their small sizes & low power consumption. It operates on input voltages. on the contrary, BJT operates on input current.
The schematic design of NAND gate using NMOS transistor is given below:
This NAND gate design using Two NMOS shows that they are connected together in series & the drain of first NMOS is connected to a resistor R, which is connected to supply voltage Vdd. The source of the second NMOS is connected to ground.
Input is directly applied to its gate, it does not need input resistor because it operates on input voltage rather than the input current.
The output is taken between the resistor R & the drain of the first NMOS.
Case 1
When both of the input logic is Low i.e. I_{1 }& I_{2 }= 0v, both NMOS switches OFF & the current path from Vdd to GND breaks & a conducting path from Vdd to Output is established. Thus the output becomes Vdd, which is logic High.
Case 2
The second case is when one of the input is High and the other is Low i.e. I_{1} = 0v & I_{2 }= 5v. The NMOS having High gate input switches ON and the other NMOS switches OFF as its gate input is Low.
Thus the current path breaks and the output becomes connected to Vdd, which is the output of the NAND gate.
Case 3
When both of the input is High i.e. I_{1 }& I_{2 }= 5v. Both NMOS will switch ON because their gate input is logic High. The path for the flow of current from Vdd to GND completes resulting in a direct path between GND and output. So the output becomes Logic Low.
The design schematic of NAND gate using PMOS is given below:
In this design, the two PMOS are connected in parallel with each other. The drain of the PMOS is directly connected to the supply voltage Vdd & the source is connected to resistor R, which is connected to GND.
Input is applied through the gate & the output is taken between the source & resistor R.
Case 1
When both of the input is logic Low i.e. I_{1 }& I_{2 }= 0v.
Both of the PMOS will switch ON as their gate input is logic Low, resulting in creating a path for the flow of current from Vdd to GND. As a result, a direct path between Vdd & output is established. Thus the output O becomes logic High.
Case 2
When one of the input is logic high and the other is logic Low i.e. I_{1} = 0v & I_{2 }= 5v.
The PMOS having High gate input switches OFF and the other PMOS switch ON as its gate input is Low. But still, the path is complete from Vdd to GND.
So the output will still be connected to Vdd, which means that the output is logic High.
Case 3
When both of the inputs is logic High i.e. I_{1 }& I_{2 }= 5v.
The PMOS switches OFF because their gate input is logic Low. As a result, the current path from Vdd to GND breaks & the GND becomes directly connected to the output. Thus resulting in output logic Low.
CMOS (Complementary metal oxide semiconductor) is mostly used in designing a variety of logic circuit as they are most economical,
The design of NAND gate using CMOS is given below:
In this design, NMOS & PMOS are both used together.
PMOS part is known as PullUp Network (PUN) & NMOS part is known as PullDown Network (PDN).
In Pullup network part, two PMOS are connected in parallel with each other whose drain is connected to supply voltage Vdd.
In Pulldown network part, two NMOS are connected in series. The source of one NMOS is connected with the drain of the second NMOS & the Source of second NMOS is directly connected to the GND.
These both networks are connected together as shown in the figure above. The gate of one PMOS and NMOS is connected together to make one input & the output is taken between these two networks (PUN & PDN).
Case 1
When both of the input is logic Low i.e. I_{1 }& I_{2 }= 0v.
The PMOS will switch ON & NMOS will switch OFF. Only the pullup network (PUN) activates & the pulldewn network (PDN) breaks the path between Vdd & GND. As a result, it creates a conductive path from the Vdd to the Output. Due to which, the output becomes logic High.
Case 2
When one of the input is logic high and the other is logic Low i.e. I_{1} = 0v & I_{2 }= 5v.
In this case, one PMOS & one NMOS will switch ON. It will result in activating only the pullup network (PUN) which means a direct path from Vdd to output. As a result, the output becomes logic High.
Case 3
When both of the input is logic High i.e. I_{1 }& I_{2 }= 5v
The PMOS will switch OFF because the gate input is High & the NMOS will switch ON as their gate input is logic High. As a result, only Pulldown network (PDN) activates which creates a direct path from GND to output. Thus the output becomes logic Low.
IC Details
Pin configuration with details of NAND gate IC is given below:
Pin  Detail 
1  Input 1 Gate 1 
2  Input 2 Gate 1 
3  Output Gate 1 
4  Input 1 Gate 2 
5  Input 2 Gate 2 
6  Output Gate 2 
7  Ground 
8  Output Gate 3 
9  Input 1 Gate 3 
10  Input 2 Gate 3 
11  Output Gate 4 
12  Input 1 Gate 4 
13  Input 2 Gate 4 
14  Voltage Supply Vdd 
The post Digital Logic NAND Gate (Universal Gate), Its Symbols, Schematic Designs & IC Details appeared first on Electronics Engineering.
]]>The post Digital Logic NOT Gate (Inverter), Its Symbols, Schematic Designs & IC Details appeared first on Electronics Engineering.
]]>
A Digital logic gate which produces logic True when its input is False & generates logic False when its input is True is known as NOT gate or oftenly known as Inverter.
Basically, NOT gate is an Inverter. It inverts its input logic into the output. It implements the logical inversion function. NOT gate is a single input single output gate.
There are three different symbols used for NOT gate:
The American National standard Institute symbol, it is most commonly used:
The International Electrotechnical Commission symbol:
Deutsches Institut für Normung symbol for NOT gate, which is used in Germany:
The truth table is a logic table containing the input combinations and their corresponding outputs.
Assume a NOT gate with the input I & output O.
The truth table of NOT gate is given below:
Input  Output 
0  1 
1  0 
It shows when the input is ‘1‘ or True, its output in ‘0‘ or False. And when the input is ‘0‘ or False, its output is ‘1‘ or True.
The expression for NOT gate uses the symbol ‘!‘ or ‘~‘ as shown in the expression below:
O = !I or O = ~I
NOT gate cannot be designed using diodes, because diodes do not have inversion property and they cannot invert an input signal. However, Transistor can invert any signal. So we will discuss schematic designs using different transistors.
RTL (ResistorTransistor Logic) logic uses resistors and transistors to implement any logic function. Bipolar junction transistors (BJT) are mainly of two types i.e. NPN & PNP. We will discuss the schematic designs using both of them separately in this article.
The schematic design of NOT gate using NPN transistors is:
In this schematic design, the collector of NPN is connected with resistor R2, which is connected with Vcc. The emitter of NPN is connected directly to the GND.
The output is taken from the collector terminal of NPN. The input line is connected to the base of the transistor through a resistor R1.
The supply voltage Vcc = 5v is applied to the circuit. Input True logic is 5v and False logic is 0v.
We will discuss this schematic for both cases of input logic
Case 1:
When the input is logic Low i.e. False or 0, the NPN transistor will switch off because there is no base current. As a result, there is no current flow through the transistor. So a conductive path will be established between Vcc and output, which makes the output logic High.
Case 2:
In this case, the input logic is High 5v i.e. True or 1, the NPN transistor will switch on & a conductive path from the output to ground is created. This path results in the output as logic Low.
The schematic design of NOT gate using PNP transistor is given below:
In this design, the collector is connected with Vcc of 5v & the emitter is connected to the resistor R2 which is grounded.
The output O is taken across the resistor R2 & input is applied to the base of the transistor through resistor R1.
We will discuss this design for both cases of input logic.
Case 1:
When the input is logic High, the PNP transistor will switch off because its base input is logic High. As a result, there will be no current flow because of the breaking of the current flow path.
The output becomes connected to the ground, which is logic low as output.
Case 2:
When the input is logic Low, the PNP transistor will switch on because its base input is Low. Thus the path for the flow of current will complete & there will be voltage developed across resistor R2.
This voltage across resistor R2 is taken as the output, which is logic High.
MOS logic uses Mosfets as the switching devices to implement any logic function. Mosfets such as NMOS, PMOS & CMOS are used in these designs. Mosfets are more economical because of their small sizes & low power consumption. It operates on input voltages. on the contrary, BJT operates on input current.
The schematic design of NOT gate using NMOS transistor is given below:
This NOT gate design using NMOS shows that its drain is connected to a resistor R, which is connected to supply voltage Vdd. The Source of NMOS is connected to ground.
Input is directly applied to its gate, it does not need input resistor because it operates on input voltage rather than the input current.
The output is taken between the resistor R & the drain of the NMOS.
When input logic is high, the NMOS switches on & the current path from Vdd to GND is complete. The output O is directly connected to GND, which is logic Low.
When the input is logic Low, the NMOS switch off & the current flow path breaks. Thus the supply voltage Vdd is routed as output O, which is logic High.
The design schematic of NOT gate using PMOS is given below:
In this design, the Drain of PMOS is directly connected to the supply voltage Vdd & the source is connected to resistor R, which is connected to GND.
Input is applied through the gate & the output is taken between the source & resistor R.
When the input is logic high, the PMOS will switch off & there will be no flow of current because of the breaking of the conductive path. As a result, the output will connect with GND, which is logic low.
When the input is logic Low, the PMOS will switch on. Resulting in the creating a path for the flow of current. this current flow develops a potential across the resistor R, which is taken as output O & it is logic High.
CMOS (Complementary metal oxide semiconductor) is mostly used in designing a variety of logic circuit as they are most economical,
The design of NOT gate using CMOS is given below:
In this design, NMOS & PMOS are both used together. PMOS source terminal is connected to the drain of NMOS & the drain of PMOS is connected to supply voltage Vdd. The source of NMOS is connected with GND. The gates of both transistors are joined together to make the input. The output is taken between NMOS & PMOS.
When the input is logic High, the PMOS will switch off & NMOS will switch on. As a result, it creates a conductive path from the output to the GND. Due to which, the output becomes logic Low.
When the input is logic Low, the PMOS switches on & NMOS switches off. Due to which, it creates a conductive path from the output to the supply voltage. Therefore, the output becomes logic High.
Pin configuration with details of NOT gate IC is given below:
Pin  Detail 
1  Input Gate 1 
2  Output Gate 1 
3  Input Gate 2 
4  Output Gate 2 
5  Input Gate 3 
6  Output Gate 3 
7  Ground 
8  Input Gate 4 
9  Output Gate 4 
10  Input Gate 5 
11  Output Gate 5 
12  Input Gate 6 
13  Output Gate 6 
14  Voltage Supply Vcc 
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]]>The post Digital Logic OR Gate appeared first on Electronics Engineering.
]]>The digital logic gate which generates logic True when any of its input is logic True is known as OR gate.
Logic OR gate implements the logical addition. Its output is high even if there is a single high input without caring for the other inputs.
OR gate has 1 output line & it has a minimum of 2 inputs. OR gate is also available with multiple inputs.
There are three different symbols used for OR gate.
The American National standard Institute symbol, it is most commonly used:
The International Electrotechnical Commission symbol:
Deutsches Institut für Normung symbol for OR gate, which is used in Germany:
A logic table containing different combinations of input logic & their corresponding output is called truth table.
Assume 2input OR gate with inputs I_{1}, I_{2} & the output O.
We know that logic OR gate implements logical addition which is the addition of binary numbers 0 & 1.
The logical addition of binary 2 inputs is:
I_{1 }+ I_{2 }= O
0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 1
These combinations can be represented using truthtable as shown below.
Input 
Output 

I_{1}  I_{2}  O 
0  0  0 
0  1  1 
1  0  1 
1  1  1 
The expression of OR operation uses the symbol (+) or (). Its expression is:
O = I_{1 }+ I_{2 } or O = I_{1 } I_{2}
OR gate having more than two inputs is referred as multiinput OR gate.
The output of multiinput OR gate is True when any of its input is logic True or high. It gives output false when all of its inputs are logic false.
We will discuss 3input OR gate for the sake of simplicity. Assume its input I_{1}, I_{2 }& I_{3 }and its output O.
The truth table of 3input OR gate is:
Input  Output  
I_{1}  I_{2}  I_{3}  O 
0  0  0  0 
0  0  1  1 
0  1  0  1 
0  1  1  1 
1  0  0  1 
1  0  1  1 
1  1  0  1 
1  1  1  1 
The expression for 3input OR gate is
O = I_{1} + I_{2 }+ I_{3 } or O = I_{1}  I_{2 } I_{3}
OR gate has different schematic designs depending on the available components & requirements.
In this article, we will discuss RDL (ResistorDiode Logic) & RTL (ResistorTransistor logic) schematic designs for OR gate briefly.
This logic implements any logic function using resistors and diodes. The schematic design of OR gate using RDL logic is given below.
There are two diodes whose negative terminal (cathode) is connected in parallel with a resistor. The input I_{1}, I_{2} is applied to the positive terminals (Anod) of the diodes. The resistor R is connected to the ground.
Output O is the voltage developed across the resistor R.
The input logic True or High is 5v & false or Low is 0v or ground.
We will discuss this schematic for each of the input combinations.
The first case is when both inputs are low i.e. I_{1 }& I_{2 }= 0v = ground. The schematic for such case is:
Logic 0 or Ground is applied as input I_{1 }& I_{2 }to the positive terminals of the diodes. Thus the diodes become reversed biased (switched off) & they don’t allow the flow of any current. Due to which, there is no voltage drop across R.
So the output voltage O will be zero volts, which is the voltage drop across resistor R. Thus the output is logic low or 0.
Another case is when one of the input I_{1 }or I_{2 }is true i.e. I_{1} = 0v & I_{2 }= 5v.
Logic 0 or ground applied to one of the diodes will still remain reversed biased (switched off). However, logic true or 5v to the positive terminal of the other diode will make it forward bias (switched on). Due to this one diode, the path for the flow of current will complete & there will be voltage developed across resistor R.
This voltage drop is taken as output O, which is logic true or high in this case.
The last one is when both of the inputs are logic true or high I.e. I_{1} & I_{2 }= 5v. The schematic will operate as:
When logic high of 5v is applied to the positive terminal of the diode, both of the diodes will become forward biased (switched on). This will complete the current flow path. The current flow through the circuit will result in the voltage drop across the resistor R.
The voltage drop across R is the output logic True of the OR gate.
This logic uses resistors & transistors to implement any logic function. The logic OR gate schematic design using RTL is given below:
In this schematic, two NPN transistors are connected in parallel with each other. The collector of the NPNs are connected with 5v Vs & the emitter is connected to resistor R, which is connected to the ground.
The input is applied to the gates of the NPN transistors & the output is taken across the resistor R.
This schematic operates on 5v as supply voltage Vs. The input True logic is 5v & false logic is 0v or ground.
Now we will discuss this schematic for each combination of input logic.
The first case is when both inputs are logic false or low i.e. I_{1 }& I_{2 }= 0v.
Note: NPN transistor switches on when its gate input is logic True or High & switches off when the gate input is logic false or low.
In this case, the inputs are logic low. So the ground is connected to the gates of the transistors. Due to which, the transistor switches off & the path for the flow of current breaks. As there is no current flow through the circuit, there will be no potential developed across resistor R.
The potential developed across resistor R is the output of this schematic, which is 0v. thus the output is Logic Low or False.
The second case is then one of the input is logical true & the other is false i.e. I_{1 }= 0v & I_{2 }= 5v.
In such case, one of the NPN transistors is switched on whose gate input is logic True or 5v. However, the transistor remains switched off but the path for the current flow is completed due to the switchedon transistor. There is a current flow through the circuit. Due to which, there is a potential developed across resistor R.
This potential is the output of the OR gate which is logic True or High.
The lase case is when both inputs are true or high i.e. I_{1 }& I_{2 }= 5v. The schematic will operate as:
In this case, both of the transistors are switched on because their gate input is logic True or High. The current flow path is complete through both transistors. Due to the current flow, there is a voltage drop across the resistor R.
The voltage drop across resistor R is the output of the OR gate. Which is logic true or high.
Universal gates are those logic gates which can be used to implement any logic function. The universal gates ate NAND gate & NOR gate.
The Boolean expression for NAND gate is:
NAND operation = (I_{1 }. I_{2})’
The implementation of OR gate using NAND gate is possible if we follow the expression below:
O = {(I_{1 }. I_{1})’ . (I_{2 }. I_{2})’ }’
O = {(I_{1})’ . (I_{2})’ }’
O = I_{1} + I_{2}
So the OR gate implementation design using NAND gate is:
The expression of NOR gate is:
(I_{1 }+ I_{2})’ = NOR operation
The OR gate is the inverse of NOR gate or vice versa.
O = (I_{1 }+ I_{2})’ ‘
O = I_{1 }+ I_{2}
So if we use another NOR gate as an Inverter, we can get an OR gate’s output as shown in the figure below:
The pin configuration of OR gate IC is given below:
Pin  Detail 
1  Input 1 Gate 1 
2  Input 2 Gate 1 
3  Output Gate 1 
4  Output Gate 2 
5  Input 1 Gate 2 
6  Input 2 Gate 2 
7  Vss, ground 
8  Input 1 Gate 3 
9  Input 2 Gate 3 
10  Output Gate 3 
11  Output Gate 4 
12  Input 1 Gate 4 
13  Input 2 Gate 4 
14  Voltage Supply Vdd 
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The type of Logic gate which generate logic True when all of its inputs are logic True is known as AND gate.
A digital circuit which performs or implements any Boolean operation is called logic gate. Boolean operations are logical operations based on Binary numbers. Logical multiplication, logical addition are examples of Boolean operation.
AND gate can have two or more than two inputs but it has only one output.
There are three different symbols used for AND gate.
The American National standard Institute symbol, it is the most commonly used symbol:
The International Electrotechnical Commission symbol:
Deutsches Institut für Normung symbol for AND gate used in Germany:
The truth table is a logic table, which contains different combinations of input & the output for each of the input combination.
Assume 2input AND gate with inputs I_{1} & I_{2 }& output O. As we know that AND gate implements logical multiplication. The logical operation operates on binary numbers 1 & 0.
If we apply multiplication on these inputs i.e.
I_{1 }X I_{2 }= O
0 X 0 = 0
0 X 1 = 0
1 X 0 = 0
1 X 1 = 1
This can be easily shown using a truth table as shown below.
Input  Output  
I_{1}  I_{2}  O 
0  0  0 
0  1  0 
1  0  0 
1  1  1 
The expression for AND gate operation is
O = I_{1 }. I_{2 } or O = I_{1 }& I_{2}
AND operation is denoted by dot (.) or (&) symbol.
As we know, AND gate can have more than 2 inputs. So the output of multiinput AND gate is high only when all of its inputs are High.
Consider a 3input AND gate with input I_{1}, I_{2}, I_{3 }and O as output.
The truth table for 3input AND gate is:
Input  Output  
I_{1}  I_{2}  I_{3}  O 
0  0  0  0 
0  0  1  0 
0  1  0  0 
0  1  1  0 
1  0  0  0 
1  0  1  0 
1  1  0  0 
1  1  1  1 
The expression of 3input AND gate will be
O = I_{1} . I_{2 }. I_{3 } or O = I_{1} & I_{2 }& I_{3}
There are more than one schematic designs for AND gate. In this article, we will discuss RDL (Resistordiode logic) & RTL (ResistorTransistor logic).
This logic uses only diodes & resistors to perform some operation. The schematic design of AND gate in RDL is given below:
This schematic works on 5v as V_{s} supply voltage. I_{1} & I_{2 }is the input logic for this schematic & O as taken as the output.
Let’s test the design for each combination of input logic. Take note that the input High logic is 5v & Low logic is 0v or GND (ground).
The first case is that both inputs I_{1 }& I_{2 }= 0 then the schematic will operate as:
When we apply 0v or GND to the negative terminal of the diodes, the diodes become forward biased & it starts the flow of current. There is a fixed voltage drop of diode i.e. 0.7v in case of silicon diode or 0.4v in case of germanium diode. The rest of the potential will be developed across the resistor R.
So the output O will be equal to the v_{d }= 0.4v or 0.7v, which is equivalent to the logic Low.
The second case is that if one of the input is high i.e I_{1} = 0 & I_{2 }= 1.
In such case, one of the diodes is in the forward bias because its negative terminal is connected to the GND (ground) & the other diode is in reverse bias because its negative terminal is connected with 5v.
The forward bias diode will allow the current flow through itself. Due to this flow of current, the significant voltage drop will remain across the resistor R same as in the previous case. A fixed voltage drop across diodes and the remaining potential is developed across the resistor R.
So the output voltage O= V_{d} = 0.4v or 0.7v, which is logic low. So the output is logic Low.
The third case is when both of the inputs are high i.e. I_{1 }& I_{2 }= 5v.
When High input 5v is applied to the negative terminals of the diodes, the diodes becomes reverse biased & they block the flow of current through it. As a result, the supply voltage V_{s }appears as the output O = 5v. Thus the output becomes logic High.
This logic uses transistor & resistor to implement any function. The schematic design of AND gate in resistortransistor logic is given below:
The input of this AND gate schematic is I_{1}, I_{2 }& the output is O. The input voltage supply V_{s }is 5v. The input is fed to the gates of the transistor & the output is taken across the resistor R.
The two NPN transistors are connected in series. One of their terminals (Collector) is connected to V_{s }& the other terminal (Emitter) is connected with resistor R, which is connected with GND (ground).
We will discuss this schematic for each of the input combinations.
The first case is when both inputs are logical Low i.e. I_{1 }& I_{2 }= 0v
Note: NPN transistor switches on when gate input is logic high & it switches off when gate input is logic Low
In this case, the gate voltage of both NPN transistors is 0v (ground). So the transistors will switch off & it will not allow the flow of current. The path for the flow of current from V_{s }to GND breaks.
As there is no current flow, the potential developed across the resistor R is 0v. This voltage drop is the output of the AND gate which is logical Low.
The second case is when one of the input is logical High & the other is Low i.e. I_{1 }= 1 & I_{2 }= 0.
In this case, one of the two NPN transistors is switched on, whose gate input is High. The other transistor is switched off & because of this transistor; the current cannot flow through the circuit.
The voltage developed across the resistor R is 0v because there is no current flow. This voltage is the output of the AND gate, which is logic Low or logical 0.
The last case is when both of the inputs are logical high i.e. I_{1 }& I_{2 }= 5v.
In this case, the gate input of the both NPN transistor is 5v. Due to which, both transistors are switched on. As a result, the path for the flow of the current is complete & a potential will develop across the resistor R.
The potential developed across resistor R is the output of the AND gate, which in this case is 5v. Thus the output of the AND gate becomes logical High or Logical 1.
Universal gates are gates which can be used to implement any logic function.
There are two universal gates i.e. NAND gate & NOR gate.
The expression for NAND gate is:
NAND operation = (I_{1 }. I_{2})’
The AND gate can be Implemented using NAND gate if we implement the following expression. The output O will be:
O = (I_{1 }. I_{2})’ ‘
O = I_{1 }. I_{2}
Thus it is clear that the negative or invert of NAND is AND gate as shown in the figure below.
The expression for NOR gate is:
(I_{1 }+ I_{2})’ = NOR operation
The expression for AND gate using NOR gate is:
O = {(I_{1 }+ I_{1})’ + (I_{2 }+ I_{2})’ }’
O = {(I_{1})’ + (I_{2})’ }’
O = I_{1} . I_{2}
So the Implementation of AND gate use 3 NOR gates as shown in the figure below.
The pin configuration of AND gate IC is given below.
Pin  Detail 
1  Input 1 Gate 1 
2  Input 2 Gate 1 
3  Output Gate 1 
4  Input 1 Gate 2 
5  Input 2 Gate 2 
6  Output Gate 2 
7  Ground 
8  Output Gate 3 
9  Input 1 Gate 3 
10  Input 2 Gate 3 
11  Output Gate 4 
12  Input 1 Gate 4 
13  Input 2 Gate 4 
14  Voltage Supply Vcc 
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Quantization is the process of mapping continuous amplitude (analog) signal into discrete amplitude (digital) signal.
The analog signal is quantized into countable & discrete levels known as quantization levels. Each of these levels represents a fixed input amplitude.
During quantization, the input amplitude is round off to the nearest quantized level. This rounding off is known as quantization error. Quantization error can be reduced by increasing the numbers of quantization levels.
The figure below represents an analog signal. During quantization, the analog signal’s amplitude is sampled and discretized into fixed quantization levels.
In this example, we have used 8 quantization levels. The quantization results in the loss of information. The space between two adjacent levels is known as step size.
Step size = V_{ref}/number of levels.
V_{ref }represents the maximum amplitude being represented.
If the stepsize is large then the quantization error will be high. In another word, the loss of information goes higher as the step size gets bigger.
There are two types of quantization.
The type of quantization in which the quantized levels are uniformly spaced is known as uniform quantization. In uniform quantization, each step size represents a constant amount of analog amplitude. it remains constant throughout the signal.
The example of uniform quantization is given below,
In this example, the space between any two adjacent step or levels represents 1volt amplitude.
The type of quantization in which the space between the quantized levels is nonuniform & has logarithmic relation is called nonuniform quantization.
In nonuniform quantization, the analog signal is first passed through a compressor. The compressor applies a logarithmic function on the input signal. The input signal has a high difference between its low and high amplitude. In the output signal, the low amplitudes get amplified and the high amplitude levels get attenuated, Thus making a compressed signal.
Suppose the input signal’s amplitude is m & m_{p }is the peak amplitude of the signal. Y is the output signal. Then the compression graph looks like:
As you can see from the graph, that the small input levels Δm are mapped onto bigger output levels Δy. And the higher input levels are mapped onto smaller output levels.
There are two laws for compression
μ law is a compression algorithm used for nonuniform quantization. The expression of μ law is
y = (ln(1 + μ(m/m_{p})))/ (ln(1 + μ))
Where μ is the compression parameter and m is the input amplitude & m_{p }is the peak amplitude of the input signal.
When μ=0, then there is no compression and the quantization becomes uniform. The characteristic graph for μ Law is given below:
This graph shows that if the compression parameter μ is higher than the input signal is more compressed.
Alaw is another algorithm for compression of an analog signal for nonuniform quantization. The expression for Alaw is:
Where A is the compression parameter. When A=1, then the quantization is uniform because there is no compression. The characteristics graph is given below.
Both laws are applicable with some tradeoffs.
Sampling is an important step in analog to digital conversion. The taking or capturing of samples of input analog amplitude is called sampling.
The sampling rate is the number of samples taken in the duration of one second. it is measured in hertz or sample per second. The continuously varying amplitude of an analog signal is also continuous in time. So it needs to be sampled at a fixed rate. This rate is called sampling rate or sampling frequency. Example of sampling:
This signal is sampled at a sampling rate of 2 samples per second or 2 Hz.
Sampling rate plays important role in the perfect conversion from analog to digital and reconstruction of an analog signal from the digital signal.
Sampling rate should not be very low or very high. In both cases, the converted signal is not what we want to achieve. If the sampling rate is low than the original signal is destroyed and if the sampling rate is very high then it’s not economically beneficial.
If the analog signal is sampled at a frequency lower than the required rate then the sampled signal does not appear to be anything like the original signal. And the reconstruction of the original signal becomes impossible. Such case is called aliasing as shown in the figure below.
In this example, a sinusoidal signal is sampled at a rate of 3/4 of its frequency. which is very lower than its required rate. The reconstructed signal (red signal) is recovered from the sample which does not look anything like the original signal.
The sampling rate or sampling frequency should be greater than twice the input signal’s frequency. Nyquist theorem suggests the minimum sampling rate for a signal which can be perfectly reconstructed from its samples.
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ADC stands for analog to digital converter. It is an electronic device used for converting an analog signal into a digital signal.
The analog input signal of ADC is continuous time & continuous amplitude signal. The output of ADC is a discrete time and discrete amplitude digital signal.
In the real world, every real quantity such as voice, temperature, weight etc exists in the analog state. And it cannot be processed by any digital device such as a computer or a cell phone.
These analog quantities are converted into digital form so that a digital device can process it. This conversion is done using analog to digital converter.
The analog signal is first applied to the ‘sample‘ block where it is sampled at a specific sampling frequency. The sample amplitude value is maintained and held in the ‘hold‘ block. It is an analog value. The hold sample is quantized into discrete value by the ‘quantize‘ block. At last, the ‘encoder’ converts the discrete amplitude into a binary number.
The conversion from analog signal to a digital signal in an analog to digital converter is explained below using the block diagram given above.
The sample block function is to sample the input analog signal at a specific time interval. The samples are taken in continuous amplitude & possess real value but they are discrete with respect to time.
The sampling frequency plays important role in the conversion. So it is maintained at a specific rate. The sampling rate is set according to the requirement of the system.
The second block used in ADC is the ‘Hold’ block. It has no function. It only holds the sample amplitude until the next sample is taken. The hold value remains unchanged till the next sample.
This block is used for quantization. It converts the analog or continuous amplitude into discrete amplitude.
The on hold continuous amplitude value in hold block goes through ‘quantize’ block & becomes discrete in amplitude. The signal is now in digital form as it has discrete time & discrete amplitude.
The encoder block converts the digital signal into binary form i.e. into bits.
As we know that the digital devices operate on binary signals so it is necessary to convert the digital signal into the binary form using the Encoder.
This is the whole process of converting an Analog signal into digital form using an Analog to Digital Converter. This whole conversion occurs in a microsecond.
Resolution of an ADC is the number of bits that represents the digital signal’s amplitude.
The analog signal has continuous amplitude. It can have infinite values i.e. real, floating basically any value one can imagine. On the other hand, the digital signal has a discrete and finite number of values. These discrete values are represented using binary numbers (bits).
To better understand the idea of resolution of ADC,
The figure above shows an analog signal represented in a digital form which is either 0 or 1. This is a 1bit resolution. The resolution of ADC defines its number of steps.
number of steps = 2^{n}
Where n is the number of bits. Therefore, there are 2 steps in 1bit resolution.
This figure shows the conversion of analog to digital in 2bit resolution. There are 4 steps or quantization levels.
No of steps = 2^{n} = 2^{2} = 4
This figure shows 4bit resolution. The number of steps in 4bit resolution is 16.
No of steps = 2^{n} = 2^{4 }= 16
The number of steps increases exponentially with increase in the bitresolution. It also implies that by increasing the bits of resolution the converted digital signal becomes more like the original analog signal. So ideally, we can say that a digital signal with infinite resolution is an analog signal.
The voltage difference between two adjacent steps is known as the width of the step. It is denoted by Δv.
So a single step represents a fixed voltage that is
Δv = v_{ref}/2^{n}
Where v_{ref }is the maximum voltage being converted & n represents the bits of resolution.
For example:
v_{ref }= 10.24v & n = 10 bits
Then:
Δv = 10.24/2^{10}
Δv = 10.24/1024
Δv = 0.01v
Thus the stepsize or width of the step is 0.01v. In this ADC, a single bit increase represents a 0.01v of increase in the analog input. If analog input is increased by 0.01v then the output is increased by 1 bit.
The ADC updates its value if the increase or decrease in its input voltage is greater than Δv/2. Any change less than Δv/2 will not be registered. This is known as Quantization Error.
The increase in the resolution of the ADC decreases the stepsize if the v_{ref} remain constant. Consequently, the quantization error decreases.
The number of samples taken during a single second is known as sampling rate or sampling frequency.
The sampling rate should be set according to the input signal. It should not be very low or very high.
Example of sampling:
This example shows that the sampling rate is 0.5 sec, as it takes 2 samples in one second.
If the sampling rate is very low then the resultant signal will not look anything like the original signal. In fact, it will become a different signal after reconstruction. This problem is known as aliasing.
To avoid this problem, the sampling rate should be kept higher than twice the frequency of the input signal. Antialiasing filters are also used for removing the frequency components higher than one half of the sampling rate. it blocks the aliasing components from being sampled.
Nyquist criteria suggest the minimum possible sampling rate for an analog signal which can be reconstructed successfully. If the highest frequency of the analog signal is f, the signal can be reconstructed successfully from its samples, if the samples are taken at a sampling frequency greater than 2f.
The offset in ADC is the shift in the digital output. For example, for input v_{in} = 0, the output might not necessarily be digital 0. It can be digital 5, which will be the offset of the ADC.
In the modern world of growing technology, we are dependent on digital devices. These digital devices operate on the digital signal. But not every quantity is in digital form instead they are in analog form. So an ADC is used for converting analog signals into digital signals. The applications of ADC are limitless. Some of these applications given below:
In today’s modern world almost every device has become the digital version of itself & they need to have ADC in it. Because it has to operate in digital domain which can be only acquired using analog to digital converter (ADC).
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A signal is defined as any physical or virtual quantity that varies with time or space or any other independent variable or variables.
Graphically, the independent variable is represented by horizontal axis or xaxis. And the dependent variable is represented by vertical axis or yaxis.
Mathematically, a signal is a function of one or more than one independent variables.
It depends on a single independent variable. It either varies linearly or nonlinearly depending on the expression of the signal. Examples of single variable signal are:
S(x) = x+5
S(x) = x^{2}+5 Where x is the variable
S(t) = cos(wt+ϴ) Where t is the variable
A two variable signal varies with the change in the two independent variables. Example of a two variable signal is
S(x,y) = 2x+ 5y
A signal is defined by its characteristics. It shows the nature of the signal. These characteristic are given below:
Amplitude is the strength or height of the signal waveform. Visually, it is the height of the waveform from its center line or xaxis. The yaxis of a signal’s waveform shows the amplitude of a signal. The amplitude of a signal varies with time.
For example, the amplitude of a sine wave is the maximum height of the waveform on Yaxis.
The signal’s strength is usually measured in decibels db.
Frequency is the rate of repetitions of a signal’s waveform in a second.
Periodic signals repeat its cycle after some time. The number of cycles in a second is known as Frequency. The unit of Frequency is hertz (Hz) and one hertz is equal to one cycle per second. It is measured along the xaxis of the waveform.
For example, a sine wave of 5 hertz will complete its 5 cycles in a one second.
The time period of a signal is the time in which it completes its one full cycle. The unit of the time period is Second. The time period is denoted by ‘T’ and it is the inverse of frequency. I.e.
T=1/F
For example, a sine wave of time period 10 sec will complete its one full cycle in 10 seconds.
The phase of a sinusoidal signal is the shift or offset in its origin or starting point. The phase shift can be lagging or leading. Usually, the original sinusoidal signals have 0° degree phase and start at 0 amplitude but an offset in phase will shift its starting amplitude to other than 0.
An example of 45° phase shift is given below. The signal remains same but its origin is shifted to 45°.
The phase shift can be from 0° to 360° in degrees or 0 to 2π in radians. 360° degree or 2π radians is one complete period.
The size of a signal is a number that shows the strength or largeness of that signal. As we know, a signal’s amplitude varies with respect to time. Because of this variation, we cannot say that its amplitude can be its size. To measure the signal size, we have to take into account the area covered by the amplitude of the signal within the time duration.
According to the size of the signal, there are two parameters.
The energy of the signal is the area of the signal under its curve. But the signal can be in both positive and negative region. Due to which, it will cancel each other’s effect resulting in a smaller signal. To eradicate this problem, we take the square of the signal’s amplitude which is always positive.
For a signal g(t), the area under the g^{2}(t) is known as the Energy of the signal.
This energy is not taken as in its conventional sense, but it shows the signal size. Therefore, its unit is not joule. The unit of energy depends on the signal. If it is a voltage signal then its unit will be volts^{2}/second.
The energy of a signal can be measured only if the signal is finite. The infinite signal will have infinite energy, which is absurd. A finite signal’s amplitude goes to 0 as the time (t) approaches to infinity (∞).
So it is necessary that the signal is a finite signal if you want to measure its energy.
If the signal is an infinite signal i.e. its amplitude does not go to 0 as time t approaches to ∞, we cannot measure its energy. In such case, we take the time average (Time period) of the energy of the signal as the power of the signal.
Similar to Energy of the signal, this power is also not taken in the conventional sense. It will also depend on the signal to be measured. If the signal is voltage signal, then the power will be in volts^{2}.
Just like the energy of signal, the measurement of the power of a signal also has some limitation that the signal must be of a periodic nature. An infinite and nonperiodic signal neither have energy nor power.
Signals are classified into different categories based on their characteristics. Some of these categories are given below.
The signal can be classified into analog or digital category base on their amplitude. This classification is based on only verticalaxis (amplitude) of the signal. And it does not have any relation with horizontalaxis (time axis).
The amplitude of an analog signal can have any value (including fractions) at any point in time. That means analog signal have infinite values.
However, the digital signal’s amplitude can only have finite and discrete values.
The special case of Digital signal having two discrete values is known as Binary signal. However, the number of values for amplitude in a digital signal is not limited to only two.
Analog signal is converted into Digital signal using A to D converter (ADC).
This classification is based on the horizontal axis (time axis) of the signal.
Continuous and discrete time signals should not be confused with analog and digital signal respectively.
A continuous time signal is a signal whose value (amplitude) exists for every fraction of time t.
A discrete time signal exists only for a discrete value of time t.
Remember, there is no limitation on the amplitude of the signal. That is why it should not be confused with the analog or digital signal.
A signal is Energy signal if its amplitude goes to 0 as time approaches ∞. Energy signals have finite energy.
Similarly, a signal with finite power is known as Power signal. A power signal is a periodic signal i.e. it has a time period.
An Energy signal has finite Energy but zero power. And a Power signal has finite Power but infinite Energy. So a signal can be either energy signal or power signal but it cannot be both.
An infinite signal that has no periodic nature is neither Energy nor Power signal.
A periodic signal is a signal which keeps repeating its pattern after a minimum fixed time. That time is known as Time period ‘T’ of that signal. Periodic signal does not change if it is timeshifted by any multiple of Time period “T”.
The mathematical expression for periodic signal g(t) is:
T_{0 }is the Time period of signal g(t).
Periodic signal starts from t=∞ and continues to t=+∞. A signal which starts at t=0 will not be the same signal if it is timeshifted by +T because it did not exist for negative t.
The aperiodic or nonperiodic signal is a signal which does not repeat itself after a specific time. These signals have no repetitions of any pattern.
A signal which can be represented in mathematical or graphical form is called deterministic signal. Deterministic signals have specified amplitude, frequency etc. They are easy to process as they are defined over a long period of time and we can Evaluate its outcome if they are applied to a specific system based on its expression.
The random or nondeterministic signal is a signal which can only be represented in probabilistic expression rather than its full mathematical expression. Every signal that has some kind of uncertainty is a random signal. Noise signal is the best example of random signal.
Generally, every message signal is a random signal because we are uncertain of the information to be conveyed to the other side.
Some basic operation of signals are given below
Timeshifting means movement of the signal across the time axis (horizontal axis). A time shift in a signal does not change the signal itself but only shifts the origin of the signal from its original point along timeaxis.
Basically, addition in time is time shifting. To timeshift a signal g(t), t should be replaced with (tT), where T is the seconds of timeshift. Therefore, g(tT) is the timeshifted signal by T seconds.
Time shift can be rightshift (delay) or leftshift (advance).
If the timeshift T is positive than the signal will shift to the right (delay). For example, the signal g(t4) is the shifted version of g(t) with 4 seconds delay.
If the timeshift T is negative than the signal will shift to the left (advance). The signal g(t+4) is the shifted version of g(t) with 4 seconds to the left.
Time scaling of a signal means to compress or expand the signal. It is achieved by multiplying the time variable of the signal by a factor. The signal expands or compresses depending on the factor.
Suppose a signal g(t) than its scaled version is g(at).
If the factor a>1 then the signal will compress. And the operation is called signal compression. Compressing a signal will make the signal fast as it becomes smaller and its time duration become less.
If a<1 then the signal will expand. And the operation is called signal dilation.
After scaling, the origin of the signal remains unchanged. Expanding the signal will make the signal slow as it becomes wider and covers more time duration.
In time inversion, the signal is flipped about the yaxis (vertical axis). The resultant signal is the mirror image of the original signal.
Time inversion is a special case of timescaling in which the factor a=1. Therefore to invert a signal, we replace it’s (t) with (t).
Mathematically, the timeinvert of signal g(t) is g(t).
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]]>The type of modulation in which the amplitude of the carrier signal varies linearly with respect to the instantaneous amplitude of the message signal is called Amplitude modulation.
There are several types of Amplitude modulations.
Double sideband is a type of Amplitude modulation in which the frequency spectrum of the message signal is symmetrically situated above & below the carrier signal’s frequency.
The upper & lower frequencies are known as sidebands of the modulated signal. Upper sideband (USB) has frequency components higher than the carrier frequency and the lower sideband (LSB) has lower frequency components than the carrier frequency.
Suppose the message signal is sinusoidal signal.
m(t) = A_{m}cos ω_{m}t
The carrier signal is a high frequency sinusoidal signal.
c(t) = A_{c }cos ω_{c}t
The Amplitude modulated DSB SC signal will be
ϕ_{DSBSC}(t) = A_{DSB} cos ω_{c}t
A_{DSB } = A_{c} + m(t)
Substituting A_{DSB }
ϕ_{DSBSC}(t) = (A_{c} + m(t)) cos ω_{c}t ……….eq(1)
ϕ_{DSBSC}(t) = A_{c }cos ω_{c}t + m(t) cos ω_{c}t
Substituting m(t)
ϕ_{DSBSC}(t) = A_{c }cos ω_{c}t + A_{m}cos ω_{m}t cos ω_{c}t
ϕ_{DSBSC}(t) = A_{c }cos ω_{c}t + A_{m}/2 cos (ω_{m }+ ω_{c}) t + A_{m}/2 cos (ω_{m }– ω_{c}) t
The modulated signal has three terms.
The first term represents the carrier signal. The second term represents the message signal’s frequency shifted to the left by ω_{c}. The third term represents the message signal’s frequency spectrum shifted to the right by ω_{c} as shown in the figure below.
Suppose the message signal’s spectrum is
The spectrum of carrier signal is
The DSB SC modulated signal’s spectrum is
The message spectrum is centered at ω_{c }having two halves. The upper half (ω_{c }+ ω_{m }) of the message spectrum is called upper sideband & lower half (ω_{c }– ω_{m }) of the message spectrum is called lower sideband. Because of these two sidebands, it is called double sideband AM transmission.
In Amplitude modulation, it describes the level of carrier signal amplitude over the level of the message signal.
According to the eq(1)
ϕ_{DSBSC}(t) = (A_{c} + m(t)) cos ω_{c}t
Substituting m(t)
ϕ_{DSBSC}(t) = (A_{c} + A_{m}cos ω_{m}t) cos ω_{c}t
ϕ_{DSBSC}(t) = A_{c} (1 + A_{m}/A_{c }cos ω_{m}t) cos ω_{c}t
ϕ_{DSBSC}(t) = A_{c} (1 + μ cos ω_{m}t) cos ω_{c}t
where μ= A_{m}/A_{c }is the modulation index.
Modulation index plays important role in traditional AM discussed in this article below.
The bandwidth B.W of DSBSC is the difference between the maximum and minimum frequency of the modulated signal.
B.W = (f_{c}+ f_{m}) – (f_{c}– f_{m} )
B.W = f_{c}+ f_{m} – f_{c}+ f_{m}
B.W = 2 f_{m}
The bandwidth of the DSBSC modulated signal is twice the bandwidth of the message signal.
Demodulation is the process of acquiring the original signal (message signal) from the modulated signal (received signal).
To demodulate a DSBSC signal, it is multiplied with the carrier signal (coherent frequency).
Assume the modulated signal is
ϕ(t) = m(t) cos ω_{c}t
Then the modulated signal will be
e(t) = m(t) cos ω_{c}t cos ω_{c}t
e(t) = ½ m(t) (1 + cos 2ω_{c}t)
e(t) = ½ m(t) +½ m(t) cos 2ω_{c}t
The demodulated signal contains two terms, a message signal and a high frequency term. The high frequency term is filtered out by passing through Low Pass Filter.
In DSBFC, the carrier signal is utilized during demodulation. The message signal is stored in the envelope of the modulated signal. In order to acquire this envelope, the amplitude of message signal in the modulated signal should not go below Zero. i.e.
A_{c }+ m(t) ≥ 0
carrier amplitude A_{c} should be adjusted to satisfy the equation.
A_{c }– A_{m} ≥ 0
A_{m }= lowest peak amplitude of message signal.
A_{c } ≥ A_{m}
1 ≥ A_{m}/ A_{c}
1 ≥ μ
where μ = A_{m}/ A_{c}
0 ≥ μ ≥ 1
Thus the modulation index μ should be between 0 & 1 for envelope detection at receiver.
DSBFC or traditional AM can be demodulated by using coherent source or envelope detector. Envelop detector is very simple and inexpensive process.
An envelope detector is a simple diode, capacitor and resistor circuit. It does not need any coherent source or any low pass filter.
The message signal is rectified out using this envelope detector.
Quadrature Amplitude Modulation is the type of Amplitude modulation in which two different message signals are transmitted on same frequency carrier with different phase shift.
The DSB modulated signal has double bandwidth of the modulating signal. To overcome excessive bandwidth, QAM is applied by sending two message signals on the same frequency carrier signal with 90° phase difference.
The block diagram of QAM is given below:
This block diagram shows modulation of two message signals. The carrier source produces carrier signal. The carrier signal with 0° phase shift is used with first message signal m_{1}(t) and the carrier signal with 90° phase shift is used with second message signal m_{2}(t). Both modulated signals are then added using summer to make a single signal having same frequency and bandwidth.
Suppose two message signals are m_{1}(t), m_{2}(t)
The carrier signal is
c(t)= cos ω_{c}t.
So the 90° degree phase shifted signal of c(t) will be
c(t)= cos (ω_{c}+90°)t = sin ω_{c}t.
So the modulated single will be
Φ_{QAM}(t) = m_{1}(t) cos ω_{c}t + m_{2}(t) sin ω_{c}t
QAM modulated signal cannot be demodulated using envelope detection technique because it contains two message signals. The messages signals are demodulated by multiplying the QAM signal with its coherent carrier signal as follows.
To get m_{1}(t), the received signal is multiplied with cos ω_{c}t.
e(t)= (m_{1}(t) cos ω_{c}t + m_{2}(t) sin ω_{c}t) cos ω_{c}t
e(t)= m_{1}(t) cos^{2} ω_{c}t + m_{2}(t) sin ω_{c}t cos ω_{c}t
e(t)= ½ m_{1}(t) (1+cos 2ω_{c}t) + ½ m_{2}(t) sin 2ω_{c}t
e(t)= ½ m_{1}(t) +½ m_{1}(t) cos 2ω_{c}t) + ½ m_{2}(t) sin 2ω_{c}t
By passing through Low Pass Filter
e(t)= ½ m_{1}(t)
To get m_{2}(t), the received signal is multiplied with sin ω_{c}t.
e(t)= (m_{1}(t) cos ω_{c}t + m_{2}(t) sin ω_{c}t) sin ω_{c}t
e(t)= m_{1}(t) cos ω_{c}t sin ω_{c}t + m_{2}(t) sin^{2} ω_{c}t
e(t)= ½ m_{1}(t) sin 2ω_{c}t + ½ m_{2}(t) (1cos 2ω_{c}t)
e(t)= ½ m_{1}(t) sin 2ω_{c}t + ½ m_{2}(t) – ½ m_{2}(t) cos 2ω_{c}t)
By passing through Low Pass Filter
e(t)= ½ m_{2}(t)
The type of Amplitude modulation, in which only single side band is transmitted thorough antenna is called single sideband communication.
Unlike DSB, the SSB modulated signal has only single sideband either upper sideband (usually) or lower sideband.
The SSB modulated signal is made from DSB signal by passing it through a bandpass filter. The bandpass filter cutoff the DSB modulated signal at ω_{c }and filter out either upper sideband or lower sideband as shown in fig below.
The bandwidth of the SSB signal is equal to the bandwidth of the message signal.
If the received signal is SSB suppressed carrier signal then the demodulator needs a coherent source. which generates the same frequency carrier as the received signal. After demodulation, the signal is passed through low pass filter to filter out highfrequency components.
If the received signal is SSB full carrier signal then it is best to use an Envelope detector or Rectifier. The SSB full carrier transmission is a type of SSB transmission in which the carrier amplitude is very large compared to message signal amplitude.
As we know that a real bandpass filter does not have a sharp cutoff and it does not filter all the frequencies outside of cutoff region. A real filter allows some frequency content outside of the cutoff region. Because of this problem vestigial sideband is implemented.
In VSB, one sideband and a little portion (25%) of the second sideband is transmitted as shown in the figure below.
The bandwidth of VSB modulated signal is greater than SSB but it is lower than DSB modulated signal. The bandwidth of VSB modulated signal is 25% greater than the bandwidth of the message signal.
B.W = f_{m} + 25% f_{m}
If the received signal is VSB suppressed carrier signal, then the demodulation only needs coherent carrier source. The rest of the demodulation process is same as SSB and DSB suppressed carrier demodulation.
If the received signal is VSB with the carrier, then an envelope detector can also demodulate the signal. The VSB full carrier needs very large carrier amplitude as compared to message signal’s amplitude.
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Boolean logic refers to the form of algebra where the variables have only 2 unique values i.e. TRUE or FALSE. These values are often used as 1 or 0 in binary language.
A Boolean function is a logical operation of one or more than one variables whose resultant is a single binary bit. It can only be either TRUE or FALSE. Boolean functions are based on boolean logic.
A digital logic gate is a device which implements any Boolean function. Some of these basic logic gates are given below:
NOT gate is a basic digital logic gate. This digital logic gate inverts its input into output. It is also known as Inverter. It is also sometimes referred to as negation buffer. NOT gate is a single input single output gate.
The logical operator for NOT is ‘!’ and it inverts its operand’s value.
The Truth table for NOT gate is:
Input  Output 
1  0 
0  1 
This digital logic gate implements the logical AND function, which is the Boolean product of two or more than two variables. AND operation is also known as a logical conjunction. In other words, the output of AND gate is TRUE when all of its inputs are TRUE.
AND function’s operator, the logical conjunction is denoted by ‘Λ’ or ‘.’.
AND gate has minimum two inputs and a single output. The truth table for AND gate is:
Input 1  Input 2  Output 
0  0  0 
0  1  0 
1  0  0 
1  1  1 
Digital logic OR Gate implements the logical OR function. Logical OR function gives TRUE output if any of its operands are TRUE. Thus, the output of OR gate is True if any of its Input is TRUE.
OR logic function is also known as inclusive disjunction. And its operator is ‘∨’ or ‘+’.
OR gate has a minimum of two inputs and a single output. The truth table for OR gate is:
Input 1  Input 2  Output 
0  0  0 
0  1  1 
1  0  1 
1  1  1 
NAND Gate is a digital logic gate which performs negative AND function. As its name suggests, NAND (NOT of AND) operation inverts the output of AND operation. In other words, the output of NAND gate is False only when all of its inputs are high.
NAND gate has minimum two inputs and a single output.
NAND gate’s truth table is
Input 1  Input 2  Output 
0  0  1 
0  1  1 
1  0  1 
1  1  0 
The digital NOR gate is a NegativeOR gate. The operation of NOR is negation or NOT of logical OR gate. In other words, the output of NOR gate is LOW when any of its input is HIGH.
It has minimum two inputs and a single output.
The truth table of NOR gate is
Input 1  Input 2  Output 
0  0  1 
0  1  0 
1  0  0 
1  1  0 
ExclusiveOR or XOR gate is a digital gate used as a parity checker. XOR gate gives output TRUE when the numbers of TRUE inputs are odd. For a twoinput XOR gate, the output is TRUE if the inputs are different. Otherwise, the gate will produce FALSE output.
The truth table of XOR gate is following
Input 1  Input 2  Output 
0  0  0 
0  1  1 
1  0  1 
1  1  0 
XNOR gate or Exclusive NOR gate is the negative or inverse of XOR gate. Generally, XNOR gate give output TRUE if it has EVEN number of TRUE inputs. The output of twoinput XNOR gate is TRUE if the inputs are same. When the inputs are different, the 2input XNOR gate produces FALSE output.
The following is the Truth table for XNOR gate
Input 1  Input 2  Output 
0  0  1 
0  1  0 
1  0  0 
1  1  1 
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